---
title: An AI Agent Designed a 2 MAC per Clock INT4 Accelerator for One Tiny Tapeout Tile, Without Spending Money
slug: ai-agent-chip-design-on-free-tiny-tapeout-flow
date: 2026-10-22
updated: 2026-10-22
author: Kai Kim
status: published
confidence: 0.62
tags: [chip-design, tiny-tapeout, sky130, ai-agents, formal-verification, int4, experiments]
categories: [experiments]
summary: Over two days the lab used an AI agent pipeline (chip lab, driven by Claude Code) to take a small dot product accelerator from a UART toy to a weight stationary INT4 design that does 2 multiply accumulates per clock in a single 1x1 Tiny Tapeout tile on SkyWater sky130. Every version closed timing at 50 MHz with DRC and LVS clean, passed gate level stress tests, and ran a real 64 to 10 digit classifier bit identical to Python. Nothing was paid for and nothing was fabricated. The current reading is that the agent's leverage comes from cheap, automatic rejection of bad candidates, and the binding constraint is the quality of the checks, not writing RTL.
key_takeaways:
  - Four versions of the same accelerator fit one 1x1 tile and went from about 0.005 to 2.0 multiply accumulates per clock, a 4x step over the first parallel pin version, all signoff clean on the free GitHub Actions flow.
  - The two ideas that each looked like 2x on paper only produced a real 4x together. Weight stationary alone failed at INT8 because result output became the bottleneck, and the pipeline measured that before any layout was spent on it.
  - The checks caught the agent's own mistakes, including a missing pin connection that made synthesis delete the weight registers and report an area 4x too small, and a host driver timeout bug that appeared only after 746 dot products.
  - Nothing here is silicon. Hardware behavior of the host side (RP2040 PIO and DMA) is co simulated against an emulator, not measured.
reading_time:
related: [falsifiable-building-one-research-loop]
changelog:
  - "2026-10-22 | 0.60 | Initial publication | Records the chip lab experiment after four versions passed the Tiny Tapeout flow"
  - "2026-10-22 | 0.62 | Added 2 bit and 1 bit activation versions (4 and 8 multiply accumulates per clock) and the tt-fit tool | Two more designs passed the same flow with gate level tests and a formal proof of the output queue"
  - "2026-10-22 | 0.62 | Corrected the tt-fit accuracy claim | Checked against 436 real shuttle projects, the first version's 2.2 point accuracy did not hold; replaced with the version 2 numbers"
  - "2026-10-22 | 0.62 | Added the classifier compiled into logic (80 multiply accumulates per clock, two tiles) and its timing counterexamples | It took four layouts to close timing, and two of them broke the pre layout timing rule"
---

# Question

Can an AI agent pipeline take a small machine learning accelerator from a specification to a layout that would pass a real tapeout check, using only free tools and free compute, and where does the work actually get hard?

This matters because chip design is usually treated as the domain least reachable by a solo builder. If an agent can carry the loop with honest verification, the cost of exploring hardware ideas drops from a team and a budget to an afternoon of compute.

# Observation

The lab built `chip-lab`, a local design lab where Claude Code drives open source tools: Icarus Verilog and Verilator for simulation and lint, Yosys for synthesis and formal equivalence, OpenSTA for timing, LibreLane for layout, and the official Tiny Tapeout GitHub Actions flow for signoff. The target was one 1x1 Tiny Tapeout tile, 161 by 111.5 micrometers on SkyWater sky130, with a 50 MHz clock.

Measured results for the four versions:

| Version | Multiply accumulates per clock | Placement utilization | Slow corner setup slack | Gate level tests |
|---|---|---|---|---|
| UART serial, INT8 | about 0.005 | 65.5% | +5.14 ns | 6 of 6 |
| Parallel pins, INT8, chained | 0.5 | 61.8% | +7.13 ns | 10 of 10 |
| Parallel pins, INT4, chained | 1.0 | 52.6% | +7.09 ns | 10 of 10 |
| Parallel pins, INT4, weight stationary | 2.0 | 76.9% | +9.43 ns | 6 of 6 |
| INT4 weights, 2 bit activations | 4.0 | 73.1% | +6.29 ns | 7 of 7 |
| INT4 weights, 1 bit activations | 8.0 | 82.5% | +5.52 ns | 7 of 7 |
| Whole classifier as logic, two tiles | 80 | 75.0% | +5.26 ns | 3 of 3 |

All four reported DRC 0, LVS 0, antenna 0 and passed the Tiny Tapeout precheck. A digit classifier layer (scikit learn digits, 64 pixels to 10 classes) ran on the chip models: 3,600 dot products bit identical to Python in every case, including on the post layout gate netlist for the INT8 version. Chip clocks for 360 images fell from 482,400 (INT8) to 252,000 (INT4) to 115,760 (INT4 weight stationary), then to 58,120 and 29,320 with 2 bit and 1 bit activations, at 95.28% and 91.39% accuracy.

Update, same day: a tile has only 8 data input pins, so once weights live on chip the only lever left is how many activations fit in a byte. A quick sweep on the digits task decided which bits to cut. Ternary or binary weights dropped accuracy to 88.9% and 58.1%; 2 bit activations cost 0.3 points. The 2 bit and 1 bit designs needed a small output queue, and a k induction proof shows it never drops a result whatever the host does.

Total spend: zero. The 70 euro tile purchase that would send a design to fabrication was deliberately not made.

# Hypothesis

An agent pipeline can reach signoff clean layouts for small accelerators on free infrastructure, and its real leverage is fast, automatic rejection of wrong candidates rather than fast writing of RTL.

# Why

Writing a pipelined multiply accumulate unit is not the hard part. Knowing that a candidate is wrong, quickly, is. `chip-lab` rejects candidates in tiers: a self checking testbench in under a second, a pre layout area and slow corner timing estimate in about a second, a formal equivalence proof for every logic restructuring, a local layout in about 75 seconds, and only then the 8 to 10 minute official flow. Each tier is cheap enough that the agent can try an idea and drop it on evidence.

The clearest example was weight stationary storage. At INT8 it looked like a 2x throughput win. The pipeline measured 0.57 multiply accumulates per clock for 17% more area, because the 3 byte result output became the bottleneck. Packing two INT4 values per byte doubled the work per vector, hid the output cost, and turned the same idea into a real 2x. The decision came from measurements, not from the plan.

# Supporting Evidence

All designs, tests and CI runs are public:

- [Browser demo](https://joonsense.github.io/tt-int4-dot-accelerator/): draw a digit and the INT4 chip's integer arithmetic classifies it; random test images show the dot products the RTL produced
- [tt-digit-classifier](https://github.com/Joonsense/tt-digit-classifier), the whole 64 to 10 classifier compiled into logic: 8 bytes in, the digit on the 7 segment display, one image every 8 clocks
- [tt-lowbit-dot-accelerator](https://github.com/Joonsense/tt-lowbit-dot-accelerator), the 8 per clock version with 1 bit activations
- [tt-fit](https://github.com/Joonsense/tt-fit), the tile and timing predictor from the pipeline, free for any Tiny Tapeout project. Its first version, fit on the lab's own 13 layouts, turned out to over predict real projects by a median 3.8 points; version 2 is calibrated on 436 real projects from three sky130 shuttles and predicted a held out shuttle with a mean error of 4.4 points
- [tt-int4-dot-accelerator](https://github.com/Joonsense/tt-int4-dot-accelerator), the 2 per clock INT4 weight stationary version
- [tt-pin-dot-accelerator](https://github.com/Joonsense/tt-pin-dot-accelerator), the INT8 chained version with the digits example on the gate netlist
- [tt-uart-dot-accelerator](https://github.com/Joonsense/tt-uart-dot-accelerator), the UART version

Every stress test was also run on a deliberately broken build, and the broken build failed every test. That is what makes a pass meaningful.

The last design also broke one of the lab's own rules. Freezing the classifier weights into logic let one pixel byte feed all 10 classes at once, 80 multiply accumulates per clock. Its pre layout timing was +4.46 ns, inside a rule that had held for 13 designs, and after routing it missed by 0.65 ns because every pixel pin fanned out to about 80 gates. Two more layouts later it closed at +5.26 ns, and the rule now has a separate, stricter line for multi tile designs. A test that checked only the predicted digit also passed a build with a wrong bias, which is why the chip now has a mode to read all 10 scores back.

The checks caught the agent's own errors. A new input pin left unconnected in the tile wrapper let synthesis delete 64 weight registers, and the area estimate came out about 4x too small; the next check that compared flip flop counts exposed it. A host driver compared its timeout against total cycles since start rather than per call, so it failed after 746 dot products; the 3,600 dot product digit run exposed it. Neither would have shown up in a short demo.

# Counter Arguments

None of this is silicon. Sky130 layouts that pass the Tiny Tapeout flow usually work, but analog effects, IO timing on the real board and test escapes are not covered by simulation.

The designs are small. A 1x1 tile holds a few thousand standard cells, and the techniques that work at this scale (exhaustive candidate sweeps, per module equivalence proofs) may not survive designs a thousand times larger.

The agent did not invent the architecture ideas. Pipelining, chaining, INT4 packing and weight stationary storage are textbook. The contribution is the loop that tested them honestly, not novel hardware.

# Current Conclusion

For small accelerators on an open PDK, an AI agent with a tiered rejection pipeline can produce signoff clean, well verified layouts at no cost, and most of the human value moves to deciding which checks must exist. Confidence 0.60, because the hardware side is unmeasured.

# Unknowns

Whether the fabricated chip would behave as simulated. Whether the RP2040 PIO host reaches the co simulated 16 MHz chip clock and about 30 million INT4 multiply accumulates per second on the real demo board. How the pipeline's cost scales past one tile.

# What Would Change My Mind

A fabricated tile from this flow failing in a way the gate level tests should have caught would lower confidence sharply. A larger design where per module equivalence proofs stop finishing in minutes would show the method's ceiling.

# Next Research

Measure the PIO host on a real Tiny Tapeout demo board. Run the same pipeline on a 2x2 tile design to see where proof and layout times grow. Track whether these public designs get forked, tested or taped out by others.

# Implications

If the loop holds, small custom accelerators become a solo builder activity: the expensive parts are judgment about verification and, at the end, a tile purchase. That shifts hardware experiments from funding decisions to research decisions.

# Related Research

This experiment applies the method in [[falsifiable-building-one-research-loop]]: build, measure, and keep the failed versions on record.

# References

- Tiny Tapeout, https://tinytapeout.com
- SkyWater SKY130 open PDK, https://github.com/google/skywater-pdk
- LibreLane, https://github.com/librelane/librelane
- Yosys, https://github.com/YosysHQ/yosys